The present invention relates generally to semiconductor processing and, more particularly to methods for etching gold layers in an IC layer stack.
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are etched from a metallization layer disposed above the substrate, are then employed to couple the devices together to form a desired circuit. Most commonly, metallization layers are made from aluminum or aluminum alloys, but there is increasing use of other metals such as copper and gold. To facilitate discussion, FIG. 1A illustrates a cross-sectional view of a prior art integrated circuit structure 100, representing the layers formed during the fabrication of a typical semiconductor IC having a gold layer.
A substrate 102 forms a base for an integrated circuit structure 100. A gold layer 104 is shown formed over the surface of the substrate 102. A hardmask layer 106 (typically an oxide layer) is disposed above the gold layer 104, and an overlying photoresist layer 108 is formed over the hardmask layer 106.
The photoresist layer 108 represents a layer of conventional resist material that may be patterned using patterned reticles and a stepper that passes light (e.g., ultra-violet light) onto the surface of the photoresist layer 108. The layers of the integrated circuit structure 100 are readily recognizable to those skilled in the art and may be formed using any number of known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To etch the hardmask layer, the photoresist layer 108 is patterned with a suitable photolithography technique, and subsequently the exposed hardmask layer is etched. FIG. 1B shows a cross-sectional view of the prior art integrated circuit structure 100 after etching the oxide hardmask layer 106 to form a hardmask for the underlying gold layer 104.
Conventionally, gold layers have been etched using a Cl2 chemistry at elevated temperatures of about 200xc2x0 C. At such high temperatures, an oxide hardmask must be employed because of the relatively high etch rate ratio of gold to oxide and the low selectivity to organic photoresist. FIG. 1C shows a cross-sectional view of the prior art integrated circuit structure 100 after etching the gold layer using a Cl2 chemistry at an elevated temperature of about 200xc2x0 C. The elevated temperature Cl2 etch provides a reasonable etch rate, however, profile control is severely limited and special high temperature reactor configurations must be used.
Due to equipment design and process throughput, a lower temperature etch process is often used to etch metallization layers. However, at lower temperatures a gold etch process using an oxide hardmask is not efficient. Thus, titanium hardmask layers are typically employed to etch metallization layers at lower temperatures of about 70xc2x0 C. FIG. 2A shows a cross-sectional view of a prior art integrated circuit structure 200, representing the layers formed during the low temperature fabrication of a typical semiconductor IC having a gold layer, after etching a titanium hardmask layer 202.
The integrated circuit structure 200 includes a substrate 202, a gold layer 204 formed over the surface of the substrate 202, a titanium hardmask layer 206 disposed above the gold layer 204, and an overlying photoresist mask 208 formed over the titanium hardmask layer 206. As discussed above, the titanium hardmask layer 206 is patterned utilizing the photoresist mask 208. However, at low temperatures the Chlorine in a conventional Cl2 chemistry attacks the titanium hardmask at the same time it etches the gold layer, resulting in poor selectivity between the gold layer 204 and the titanium hardmask layer 206. Thus, the titanium hardmask is etched away before the gold layer plasma etch process is finished, resulting in a damaged gold layer 204 after plasma etch, as shown in FIG. 2B.
In view of the forgoing, what is needed are improved methods and apparatuses for etching a gold layer utilizing a titanium hardmask. Further, there is a need for methods and apparatuses that allow etching of a gold layer at conventional or near conventional lower electrode temperatures.
The present invention fills these needs by providing a gold etching chemistry that can be used at conventional or near conventional electrode temperatures and provides greatly improved mask selectivity with respect to a titanium hardmask. In one embodiment, a method for anisotropically etching a gold layer through an aperture in a hardmask is provided. A substrate is introduced into a processing chamber in preparation for a gold etch. The substrate includes a gold layer, a hardmask layer containing titanium formed above the gold layer, and an overlying photoresist mask disposed above the hardmask layer. The hardmask layer is then etched through the photoresist mask to create a hardmask for the underlying gold layer. Finally, a plasma is created within the processing chamber from an oxidizing gas and an etching gas. The etching gas is preferably a hydrochloric acid containing gas which may contain a chlorine containing gas. In addition, N2 may also be provided. The plasma is then used to etch the gold layer through the hardmask.
In another embodiment, a system for etching gold layers is provided. The gold layer etch system includes a chamber receptive to a substrate having a gold layer and an overlying hardmask containing titanium. Also included in the gold etch system is a gas inlet mechanism connecting an oxidizing gas and an etching gas source to the chamber. The etching gas is preferably a hydrochloric acid containing gas which may contain a chlorine containing gas. In addition, N2 may also be provided. Further included in the system is a pair of electrodes disposed within the chamber, and an RF generator coupled to the electrode pair so that a plasma is formed with the oxidizing gas and the etching gas which etches exposed portions of the gold layer through the hardmask.
In yet a further embodiment of the present invention an integrated circuit having a gold layer formed in a plasma processing chamber is disclosed. In this embodiment, the substrate, from which the integrated circuit is later formed, is introduced into a processing chamber. The substrate includes an underlying gold layer, a hardmask layer containing titanium, and an overlying photoresist mask formed above the hard mask layer. The hardmask layer is then etched through the photoresist mask to create a hardmask. Next, a plasma is created within the processing chamber from an oxidizing gas and an etching gas. The etching gas is preferably a hydrochloric acid containing gas which may contain a chlorine containing gas. N2 may also be provided. The plasma is then used to etch the gold layer through the hardmask. Finally, the substrate is further processed to form an integrated circuit.
Advantageously, the improved titanium hardmask selectivity of the present invention allows the etching of a gold layer at conventional or near conventional lower temperatures, thus avoiding the need for special high temperature reactor configurations. This and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following description and a study of the various figures of the drawings.